Priority is claimed from Japanese Patent Application No. 2000-292578 filed Sep. 26, 2000, the contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention generally relates to relates to a method of designing a clock wiring, and more particularly, but not limited to, a method of designing a clock wiring, where a layout design makes a function block hierarchical. The present application is based on Japanese Patent Application No. 292578/2000, which is incorporated herein by reference.
2. Description of the Related Art
With the advance of semiconductor technology in recent years, an LSI (large-scaled semiconductor integrated circuit) is becoming increasingly high in speed, high in integration, and high in scale. In particular, in a logic circuit, an LSI chip is designed by a so-called deep sub micron design rule of 0.35 xcexcm or less. There are many high integrated chips using clock frequencies in a range from several hundreds MHz to several GHz.
In the high-speed LSI of this type, it is important to reduce a difference in a clock delay time between functional circuits which causes malfunction, that is, a clock skew.
Generally, as a method of designing a clock transmission wiring (hereinafter referred to as xe2x80x9cclock wiringxe2x80x9d or xe2x80x9cclock wiring methodxe2x80x9d), a method has been employed that includes conducting a clock tree synthesis from an output terminal of a clock generating circuit to a cell group, which is a functional block to which a clock is supplied. However, an increase in the scale of LSI devices in recent years results in an increase in the number of processes for conducting a layout design and a processing period thereof, so that the conventional design method includes a huge number of processes and a long processing time for designing a single layout.
As is well known, the LSI design process is roughly divided into a functional design for designing the operation to be realized by a functional block having functional parts, a logic design for converting the functional block into a logic circuit, and a layout design for converting the logic circuit into a mask pattern.
When the layout design of the LSI chip takes a wiring delay time into consideration, there is widely employed a layout design method which is a so-called top down system, in which the functional block is made hierarchical.
The functional block is conventionally separated into two hierarchies, a superior hierarchy (hereinafter referred to as xe2x80x9ctop levelxe2x80x9d) and an inferior hierarchy (hereinafter referred to as xe2x80x9cmacroxe2x80x9d). A hierarchy design process for obtaining the layouts within each of the top level and the macro, individually, is first used to obtain the layout of the top level.
In order to develop the LSI at a low cost and in a short period of time, it is necessary to reduce the clock skew in the case of conducting the layout design method of the top down system.
Referring to FIGS. 1A to 1C, showing a first conventional method of designing a clock wiring disclosed in Japanese Patent Application Laid-open No. Hei 4-148376, the functional block, to which the clock wiring is applied, includes an output block 1 of a clock net and two macros 2, 3, where top level wirings are clock wirings from the output block 1 of the clock net to two macros 2 and 3. Initially, straight lines 7 and 8, connecting an output terminal (hereinafter referred to as xe2x80x9cclock output terminalxe2x80x9d) 11 disposed in the output block 1 of a clock net to the respective centers 25 and 35 of macros 2 and 3, are drawn to obtain cross points 201 and 301 of the straight lines 7, 8 and to obtain the respective peripheral edges of the macros 2 and 3.
Then, as shown in FIG. 1B, the cross points 201 and 302 on the peripheral edges of the macros 2 and 3 are obtained on the basis of the longest distance between the clock output terminal 11 and the crosses on the peripheral edges of the macros 2 and 3. Finally, the arranging process and the wiring process within the macro are conducted with the cross points 201 and 302 being used as the respective outer (clock) terminal positions of the macros 2 and 3, as shown in FIG. 1C. Through the above processes, the wirings between the clock output terminal 11 and the respective clock terminals (cross points) 201 and 302 of the macros 2 and 3 become equal in length to each other. When cells are arranged within the respective macros 2 and 3, the cells 203 and 303 connected to the clock terminals 201 and 302 (hereinafter referred to as xe2x80x9cclock terminal connection cellsxe2x80x9d) are disposed in the vicinity of the clock terminals 201 and 302, to thereby make the respective distances from the clock output terminal 11 to the clock terminal connection cells 203 and 303, of the respective internal clock terminals 201 and 302, equal to each other, thereby eliminating the clock skew.
However, in the first conventional clock wiring designing method, because no input/output separation buffer is added in the vicinity of the clock terminal, and because a delay model of the macro per se is not produced, the delay calculation of the top level, which is necessary for the layout design of the top down system, cannot be conducted with a high precision. The delay calculation of the top level means a delay calculation between the clock output terminal 11 and the respective clock terminal 201 and 302.
Namely, in the case where the clock wirings of the top level are made equal in length to each other, delay values from the clock output terminal 11 to the respective clock terminals 201 and 302 are different from each other due to a difference in the capacitance between the adjacent wirings caused by a difference of the wirings adjacent to the clock wiring, etc. As a result, even if the clock terminal connection cells 203 and 303 are arranged in the vicinity of the terminals 201 and 302 when the arrangement within the macro is conducted, the respective clock delays, of the clock output terminal 11 and a plurality of clock terminal connection cells 203 and 303 within the macro, are not equal to each other, and the clock skew may be large.
Also, in the case of conducting the delay calculation of the top level, because the functional block (cell) within the macro is not yet arranged, the delay calculation of the top level, which takes into consideration the accurate load after the arrangement within the macro is wired, cannot be conducted.
The flowchart of FIG. 2 illustrates a second conventional method of designing the clock wiring. A macro arrangement is first conducted (Step P1), and the terminal position of the top level is determined (Step P2). Then, the CTS (clock tree synthesis) of the top level is conducted, so that the clock skewings between the clock output terminal and the respective clock terminals of the macros coincide with each other (Step P3), the arrangement of the top level is implemented (Step P4), and the information on the resistors R and the capacitors C of the respective wirings (hereinafter referred to as xe2x80x9cRC informationxe2x80x9d) F101 is extracted.
After Step P2, the arrangements within the respective macros are conducted (Step P11), the CTS within the macros is conducted so that the respective macro delays become equal to each other (Step P12), the wiring within the macros is implemented (Step P13), and an information of a resistance and a capacitance (hereinafter a RC information) F102 of the respective wirings within the macro is extracted.
The static timing, between the clock output terminal and the clock terminal connection cell within the macro, is determined on the basis of the RC information F101 and F102 (Step P5), and it is confirmed whether the clock skew is within a given standard value or not (Step P6).
If the confirmation result in step P6 is not acceptable, the delay is adjusted by changing the drive capability of a buffer added to the CTS and adding the buffer or the like (Step P6), and Steps P5 and P6 are conducted again.
When the confirmation result in step P6 is acceptable, the clock wiring is completed.
In a second conventional method of designing the clock wiring, when the CTS within the top level (Step P3) and the CTS within the macro (Step P12) are implemented, a load within the macro is not determined.
For that reason, the following events occur. That is, the input terminal capacitance of the buffer with the maximum drive capability is loaded to conduct the CTS of the top level, the timing is analyzed after the layouts within the top level and the macro are completed, and, if the clock skew is not acceptable, the delay is adjusted by changing the drive capability of the buffer added in the CTS, adding the buffer or the like, as described above. Then, the timing is analyzed again, and the clock skew is confirmed.
As a result, it is necessary to conduct a plurality of timing analyses after the layout is completed, in addition to an analysis after the change of the buffer drive capability and the change of the layout for buffer addition, and the number of processes and the processing time increase.
Further, in a third conventional method of designing the clock wiring for deleting the clock skew, the most superior layer is set as an exclusive clock wiring layer and a capacitance between the adjacent wirings is reduced to reduce the clock skew.
However, because the third conventional clock wiring designing method always requires the exclusive clock wiring layer, even in the case where the wiring congestion caused by implementing the clock wiring does not occur, it is necessary to increase the number of wiring layers only for the clock. As a result, the number of wiring layers which are not always required increases to thereby increase the costs.
In the above-described first conventional method of designing the clock wiring, because no input/output separation buffer is added in the vicinity of the clock terminal, and no delay model of the macro per se is prepared, the delay of the top level, which is necessary for the layout design of the top down system, cannot be calculated with a high precision. As a result, even in the case where the clock wirings of the top level are made equal in length to each other, the delay values of from the clock output terminal to the clock terminals of the respective macros are different due to a difference in the capacitance between the adjacent wirings connected to the clock wiring. Thus, even if the clock terminal connection cell is disposed in the vicinity of the terminal when the arrangement within the macro is conducted, the respective clock delays between the clock output terminal and a plurality of clock terminal connection cells within the macro are not made equal to each other, to thereby lead to a defect that the clock skew may be increased.
Also, in the case where the top level delay is calculated, because the functional block within the macro is not arranged, there is a defect that the delay of the top level cannot be calculated taking into consideration the accurate load after the arrangement within the macro is wired.
Further, in the second conventional clock wiring designing method, the load within the macro is not determined at the time of implementing the CTS within the top level and the macro. Therefore, in the case where the clock skew is not acceptable, as a result of analyzing the timing and confirming the clock skew after the layout within the top level and the macro, because the delay is adjusted by changing the drive capability of the buffer added to the CTS, because the buffer or the like is added, and because the timing analysis and the clock skew confirmation are conducted again, it is necessary to conduct a plurality of timing analyses after the layout is completed in addition to the analyses after the change of the buffer drive capability and the change of the layout for buffer addition. As a result, the number of processes and the processing time increase.
In addition, because the third conventional clock wiring designing method requires the layer only for the clock wiring, even in the case where the wiring congestion caused by implementing the clock wiring does not occur, it is necessary to increase the number of wiring layers only for the clock. As a result, the number of wiring layers which are not always required increase to thereby increases the costs.
A method of designing a clock wiring, which does not require a plural number of timing analyses after changing or completing a layout, and which is capable of lessening the clock skew without using an exclusive clock wiring layer, is needed.
According to a first aspect of the present invention, there is provided a method of designing a clock wiring, in the LSI layout design of a top down system in which a functional block is sectioned into two hierarchies, consisting of a top level which is a superior hierarchy and a macro which is an inferior hierarchy. The layout of the top level is first conducted by using a hierarchy designing method that conducts the respective layouts within the top level and the macro, individually, characterized in that a delay model of the macro is prepared in advance, and characterized in that the delay of the top level is calculated by using the delay model, to thereby reduce the clock skews between a plurality of macros to which clocks are supplied, within the functional block to be designed.
According to a second aspect of the present invention, there is provided a method of designing a clock wiring, in which the delay model of the macro is prepared by adding the buffer logic of a library cell to a clock terminal description in a net list within the macro, and in which a buffer of the same drive capability corresponding to the buffer logic is disposed in the vicinity of the clock terminal at the time of layout of the macro.
According to a third aspect of the present invention, there is provided a method of designing a clock wiring in the LSI layout design of a top down system, in which a functional block is sectioned into two hierarchies, consisting of a top level which is a superior hierarchy and a macro which is an inferior hierarchy. The layout of the top level is first conducted by using a hierarchy designing manner that performs the respective layouts within the top level and the macro, individually, the method including:
a macro clock terminal determining step of setting a clock terminal that receives the supply of the respective clocks of the non-arranged first and second macros, where the arrangement within the macro is not wired;
a wiring path determining step of determining a wiring path by performing rough wiring between the clock output terminal, and the respective first and second clock terminals set in the macro clock terminal determining step;
a top level wiring step of extracting RC information, which is information on the resistors and capacitors of the respective wirings, by wiring the clock output terminal and the respective first and second clock terminals on the basis of the wiring path determined in the wiring path determining step;
a delay model preparing step of preparing the respective delay models of the first and second macros;
a top level delay calculating step of analyzing the static timing, between the clock output terminal and the respective first and second clock terminals, on the basis of the RC information and the delay model, in order to calculate first and second delay values, which are clock delay values between the clock output terminal and the respective first and second macros;
a delay difference calculating step of calculating clock delay differences between the clock output terminal, and the respective first and second macros obtained from the first and second delay values;
a buffer arranging step of arranging the buffer, of the same drive capacity corresponding to a buffer logic, in the vicinity of the respective first and second clock terminals at the time of layout within the respective first and second macros;
an in-macro arranging step of arranging the first and second macros, respectively; and
an in-macro clock arranging step of performing a clock wiring by a clock tree synthesization within the respective first and second macros based on the clock delay difference.
According to a fourth aspect of the present invention, there is provided a method of designing a clock wiring, in which the macro clock terminal determining step draws first and second straight lines that connect the clock output terminal of an output block to the respective centers of the first and second macros to obtain first and second cross points, which are cross points of the first and second straight lines and the respective peripheral edges of the first and second macros. The macro clock terminal determining step also sets the respective first and second clock terminals of the first and second macros to the respective first and second cross points, respectively.
Further, according to a fifth aspect of the present invention, there is provided a method of designing a clock wiring by providing a delay model. A delay model preparing step adds the buffer logic of a cell group in a library cell descriptive file to the clock terminal in the in-macro net list within the first and second macros.
Further, according to a sixth aspect of the present invention, there is provided a method of designing a clock wiring, in which the functional block includes:
a clock net including an output block with a clock output terminal for a clock output;
a first and second macros including first and second clock terminals for the clock input; and
clock wirings extending to the first and second macros from the output block which is the top level wiring.
According to a seventh aspect of the present invention, there is provided a method of designing a clock wiring in the LSI layout design of the top down system, in which a functional block is sectioned into two hierarchies consisting of a top level which is a superior hierarchy, and a macro which is an inferior hierarchy. The sectioning provides hierarchy, and the layout of the top level is first conducted by using a hierarchy designing procedure that conducts the respective layouts within the top level and the macro, individually, the method comprising:
a clock terminal determining step of setting a clock terminal that receives the supply of the respective clocks of the non-arranged first and second macros, where the arrangement within the macro is not wired, and where an already-arranged third macro is an arrangement within the macro that has been wired;
a wiring path determining step of determining a wiring path by performing rough wiring between the clock output terminal and the respective first, second and third clock terminals which were set in said clock terminal determining step;
a top level wiring step of extracting RC information, which is information on the resistors and capacitors of respective wirings, by wiring between the clock output terminal and the respective first and second clock terminals on the basis of the wiring path determined in the wiring path determining step;
a delay model preparing step of preparing respective delay models of the first and second macros, and extracting a delay value of the third macro from third macro wiring information in order to prepare a delay model including a third macro delay value;
a top level delay calculating step of analyzing the static timing between the clock output terminal and the respective first and second clock terminals on the basis of the RC information and the delay model, in order to calculate first and second delay values, which are clock delay values between the clock output terminal and the respective first and second macros;
a delay difference calculating step of calculating clock delay differences between the clock output terminal and the respective first and second macros using said first and second delay values;
a buffer arranging step of arranging the buffer of a same drive capacity, corresponding to a buffer logic in the vicinity of the respective first and second clock terminals at the time of layout, within the respective first and second macros;
an in-macro arranging step of arranging the first and second macros so that the delay value between the cell group within the third macro and the clock output terminal becomes equal to each corresponding delay value for the first and second macro; and
an in-macro clock wiring step of performing a clock wiring using a clock tree synthesizing method within the first and second macros, based on the clock delay difference.
Still further, according to an eighth aspect of the present invention, there is provided a method of designing a clock wiring in which the functional block includes:
a clock net including an output block that uses the clock output terminal for a clock output;
first and second macros that use the first and second clock terminals for the clock input, and for the already-arranged third macro with an arrangement that has been wired within the macro having a third clock terminal; and
clock wirings extending to the first, second and third macros from the output block which is said top level wiring.
Yet still further, according to a ninth aspect of the present invention, there is provided a method of designing a clock wiring, in which the clock wiring uses third buffers for driving the first and second buffers, the clock wiring being added to the respective first and second clock terminals by being inserted between the clock output terminal and the first and second clock terminals.
Yet still further, according to another embodiment of the present invention, there is provided a method of designing a clock wiring, in which said functional block includes:
a clock net including an output block with the clock output terminal being used for a clock output;
where the first and second macros use the first and second clock terminals for the clock input, respectively;
clock wirings extending to the first and second macros from the output block which is the top level wiring; and
a control circuit for outputting a control signal in accordance with the setting of a predetermined operating condition;
wherein the clock wiring includes a logic circuit for stopping the passing of the clock in accordance with a supply of the control signal to one or both input sides of the first and second macros.